RISC System/6000 PowerPC System Architecture

Gebonden Engels 1994 9781558603448
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Samenvatting

Offers support for a wide range of products for the RISC System/6000
product line and AIX operating system, including Uni-processor (UP) and
Symmetric Multiple Processor (SMP) systems. Provides important information
for building many system features such as memory controllers with caches
and bus-to-bus bridges. RISC System/ 6000 PowerPC System Architecture
defines an architecture that allows each operating system--in particular,
the AIX operating system--to run unchanged on all systems that comply with
this architecture. It provides a consistent software interface across a
broad range of system implementations and offers all hardware/software
dependencies necessary for a successful system identification,
configuration and performance tuning process.

An important reference for all programmers and product development
engineers who are developing software and hardware products for the
RISC/System 6000 PowerPC systems. Also useful for system programmers
involved in operating system design, system integrators building products
and parts for the system family, and anyone interested in porting other
operating systems to the RISC System/6000 family.

Specificaties

ISBN13:9781558603448
Taal:Engels
Bindwijze:Gebonden

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Inhoudsopgave

Chapter 1 Introduction <br>Chapter 2 PowerPC Processor Architecture <br>Chapter 3 Architected system Memory Map <br>Chapter 4 Bring-Up and Configuration Architecture <br>Chapter 5 NVRAM Contents and Mapping <br>Chapter 6 Bus Unit Controller (BUC) Architecture <br>Chapter 7 IOCC Architecture <br>Chapter 8 System Resources <br>Chapter 9 External Interrupt Architecture <br>Chapter 10 System Exception Processing <br>Chapter 11 System Bus Architecture <br>Chapter 12 Bring-Up Function and IPLCB <br>Chapter 13 Vital Product Data (VPI) <br>Chapter 14 AIX Based Diagnostics Requirements <br>Appendix A Processor Dependencies <br>Appendix B Standard I/O Interface <br>Appendix C Target Market Categories <br>Appendix D Memory Controller Example <br>Appendix E System Exception Implementation Examples <br>Appendix F IPLCB Example <br>Appendix G AIX Dependencies on the IPLCB <br>Appendix H AIX Command and Event Indicators <br>Appendix I Power IOCC Arch. vs PowerPC IOCC Architecture <br>Appendix J 32/64 Bit BUC Arch. Differences & Considerations <br>Appendix K Big-Endian and Little-Endian Tutorial

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        RISC System/6000 PowerPC System Architecture